Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A Fin field-effect transistor (FinFET) is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET the transistor channel is formed along the vertical sidewalls of the fin or on both vertical sidewalls and the top horizontal plane of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
FinFETs provide a promising candidate for small line width technology (e.g., approximately 22 nm and below) because of their excellent short channel effect control and scalability. To be advantageous for general purpose applications, it is desirable for FinFETs to have different threshold voltages (Vt) that can be used for different circuit functionalities. However, manufacturing FinFETs with different threshold voltages is difficult. Because the channel or “fin” width is on the order of 5-20 nm, this dimension makes it ineffective to adjust Vt by changing channel doping concentration. Moreover, channel doping could degrade mobility, which may impact FinFET performance One possible way to obtain FinFETs with different Vt is to utilize different gate stack materials in High-K-Metal-Gate FinFET technology. However, multiple gate stack processes that are needed to produce FinFETs with different Vt are complex and expensive in the manufacturing process. Another way to obtain different Vt is through body bias. For example, in a conventional surface channel nFET, negative body bias increases Vt while positive body bias lowers Vt.
Methods have proposed to introduce a body contact to FinFET structures; however, these methods are either very complicated, non-practical in manufacturing, or the FinFET device characteristics are severely affected. For example, it has been proposed to use silicon epitaxy to connect bulk silicon of a semiconductor substrate to a poly gate, where a fin is formed overlying the bulk silicon of the semiconductor substrate. However, such methods are incompatible with replacement metal gate (RMG) techniques and require silicon epitaxy to be isolated to a contact region of the poly gates to the bulk silicon of the semiconductor substrate, and the body contacts are physically isolated from direct contact with the fin. Prior efforts to form body contacts for FinFETs have avoided formation of the body contacts on the fins due to doping of the fins to form source and drain regions for the FinFETs, and because the body contacts cannot be in direct physical contact with source and drain regions of the FinFETs while maintaining operability thereof.
Accordingly, it is desirable to provide FinFET devices and methods of forming such FinFET devices. It also is desirable to provide FinFET devices and methods of forming FinFET devices that avoid complications associated with forming body contacts on the same fin as a transistor that is in electrical communication with the body contact. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.